1. Field of the Invention
The invention relates in general to a semiconductor process and structure, and more particularly to a method of manufacturing a metal silicide and a semiconductor structure using the same.
2. Description of the Related Art
As the integration of semiconductor device increases, the pattern and the line width in the device gradually decrease. The contact resistance of the gate and the conductive line in the device thereby increases, leading to a higher RC delay and adversely affecting the operating speed. Since the resistance of metal silicide is lower than poly silicon and the thermal stability of metal silicide is higher than a typical interconnection material, forming metal silicide on a gate can lower the resistance between the gate and the metal interconnection.
During the conventional method of forming metal silicide, after a gate, for example a poly silicon layer, is formed on a semiconductor wafer, the silicidation process of the gate includes forming a metal layer on the poly silicon layer, and then performing an annealing process to form a metal silicide on the gate. The formation of the metal silicide is also carried out for the gate on the periphery circuit region to lower the resistance between the gate and the wirings. However, the formation of the self-align metal silicide (salicide) in the conventional process on part of material is complicated, especially when the height of the levels on the cell array area and the periphery circuit area are different, leading to the degree of difficulty increasingly. In the current age of high performance requirement, the efficiency of the semiconductor process must be improved better than that of the conventional process.